车辆电子设备组合逻辑电路的功耗估计方法Power Dissipation Estimation Method for Combinational Logic Circuits of Vehicle Electronic Equipment
赵海发
摘要(Abstract):
为了实现对车辆电子设备组合逻辑电路的功耗估计,提出了一种基于概率建模的功耗估计方法.通过对CMOS电路能耗的简化模型分析,得到CMOS逻辑门消耗的平均功率与门的开关量直接相关;以及通过分析使门发生转换所满足的一组布尔函数,计算出在任意特定时间点每个门发生转换的转换概率,然后把全部门的这些概率加起来,获得整个组合逻辑电路在对应于一个时钟周期的所有时间点的开关量;最后建立起一般组合逻辑网络的功耗估计概率模型以及考虑不同延迟模型条件下的功耗估计.实验结果表明,提出的基于概率建模的组合逻辑电路的功耗估计方法相比于传统的随机逻辑仿真方法,不仅在功耗估计方面更加准确,而且实现功耗估计所执行的时间更短.这对于把功耗估计作为设计目标之一的现代组合逻辑电路的设计来说具有十分重要的意义.
关键词(KeyWords): 车辆电子设备;组合逻辑电路;功耗估;精确度
基金项目(Foundation): 国家自然科学基金项目(51375145)
作者(Author): 赵海发
DOI: 10.16393/j.cnki.37-1436/z.2020.05.007
参考文献(References):
- [1]綦声波,王圣南,刘群.STM32L水下记录仪的软硬件低功耗设计[J].单片机与嵌入式系统应用,2016,4:60-63.
- [2]胡海芝,郭慧玲.大型嵌入式电源设计中的低功耗设计方法研究[J].微电子学与计算机,2015,32(6):159-166.
- [3]刘勇聪,王建业,王海龙.高速四相时钟电路设计[J].测控技术,2017,36(9):142-144.
- [4]陈宇.集成电路功耗估计及低功耗设计综述[J].电子制作,2014,20:55-56.
- [5]赖玲庆,李东凯.CMOS静态功耗优化及估计方法研究综述[J].黑龙江科技信息,2016,27:157.
- [6]Ramanathan P,Surendiran B,Vanathi P T.Power Estimation of Benchmark Circuits using Artificial Neural Networks[J].Pensee Journal,2013,75(9):427-433.
- [7]Ganeshpure K P,Sanyal A,Kundu S.A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays[J].IEEE Transactions on Computers,2012,61(7):986-998.
- [8]Omana M,Rossi D,Beniamino E,et al.Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST[J].IEEETransactions on Computers,2016,65(8):2484-2494.
- [9]Todri A,Bosio A,Dilillo L,et al.Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation[J].IEEE Transactions on Very Large Scale Integration Systems,2013,21(5):958-970.
- [10]Fadl O S,Abu-Elyazeed M F,Abdelhalim M B,et al.Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model[J].Journal of Advanced Research,2016,7(1):89-94.
- [11]Najm F.Transition density:A new measure of activity in digital circuits[J].IEEE Transactions on ComputerAided Design,1998,12(2):310-323.
- [12]Bhatt K,Trivedi A I.Power Estimation of Switching Activity for Low-Power Implementation on FPGA[J].Programmable Device Circuits Systems,2011,3(14):803-807.
- [13]Kagliwal A,Balachandran S.Set-Cover Heuristics for Two-Level Logic Minimization[C].Hyderbad:In Proceedings of International Conference on VLSI Design,2012:197-202.
- [14]Settineri D,Falsone G.A method for the evaluation of the response probability density function of some linear dynamic systems subjected to non-Gaussian random load[J].Probabilistic Engineering Mechanics,2014,38:165-172.